Sequential logic, always_ff and nonblocking

Four lines in a clocked block, s1 <= d; s2 <= s1; s3 <= s2; q <= s3;, build four flip-flops. Change <= to = and the same four lines build one, which Yosys counts for you below. A clocked block describes registers, and the kind of assignment decides how many there are and when each one changes.

You will model registers with always_ff and nonblocking assignments, see what blocking assignments do to them, write synchronous and asynchronous resets and enables, read a waveform edge by edge, and predict the flip-flop cells that synthesis picks. The simulations come from Icarus Verilog 13.0 and Verilator 5.052, and the cell counts from Yosys 0.69.

Nonblocking assignments make a clocked block a chain of flip-flops

always_ff @(posedge clk) runs its body at each rising edge of clk, and each variable it writes becomes a flip-flopflip-flop: A storage element that takes the value of its input at a clock edge and holds it until the next edge. A register is a row of flip-flops clocked together.: it takes a new value at the edge and holds it until the next one. Real flip-flops clocked by one edge all capture their inputs as they were just before it, and a nonblocking assignmentnonblocking assignment: An assignment written with <= that reads its value at once but applies it only after every process woken at the same time has run, so all of them read the old values. More in “Thinking in hardware: concurrency and 4-state logic”, <=, gives the simulation the same rule: every right side is read first, and the updates land together afterwards. shift4.sv uses it for a shift registershift register: A chain of flip-flops clocked together, each loading the previous one's value at every edge, so that data moves one stage per clock cycle. of four stages:

// A 4-stage shift register: each clock edge moves every bit one stage on.
`default_nettype none

module shift4 (
  input  logic clk,
  input  logic d,
  output logic q
);
  logic s1, s2, s3;

  always_ff @(posedge clk) begin
    s1 <= d;
    s2 <= s1;
    s3 <= s2;
    q  <= s3;
  end
endmodule

`default_nettype wire

The order of reading and writing is the whole idea, so watch it on one edge. The program below models the four stages as a list holding a 1 in s1, applies one edge with d = 0, first the blocking way and then the nonblocking way, and lets you step through every line:

# One rising edge of a 4-stage
# shift register, with d = 0.
stages = [1, 0, 0, 0]  # s1 s2 s3 q
d = 0

# Blocking: each line reads what
# the line above has just written.
b = stages.copy()
b[0] = d
b[1] = b[0]
b[2] = b[1]
b[3] = b[2]
print("blocking:   ", b)

# Nonblocking: read every old
# value, then write them together.
old = stages.copy()
nb = [d, old[0], old[1], old[2]]
print("nonblocking:", nb)

blocking:    [0, 0, 0, 0]
nonblocking: [0, 1, 0, 0]

The nonblocking version moved the 1 from s1 to s2, one stage per edge. tb_shift4.sv feeds a single 1 into shift4.sv and the blocking variant beside it, then prints both outputs at every falling edge, half a period after each rising edge:

// The same four lines with blocking assignments: each stage copies the value the line above has just written.
`default_nettype none

module shift4_blocking (
  input  logic clk,
  input  logic d,
  output logic q
);
  logic s1, s2, s3;

  always_ff @(posedge clk) begin
    s1 = d;
    s2 = s1;
    s3 = s2;
    q  = s3;
  end
endmodule

`default_nettype wire

// Feeds a single 1 into both shift registers, then 0s, and prints both outputs at every falling edge.
module tb_shift4;
  logic clk, d, q, q_blocking;

  shift4          u_nb (.clk(clk), .d(d), .q(q));
  shift4_blocking u_b  (.clk(clk), .d(d), .q(q_blocking));

  initial clk = 1'b0;
  always #5 clk = ~clk;

  initial begin
    d = 1'b1;
    #10 d = 1'b0;
    repeat (5) @(negedge clk) $display("t = %0d: q = %b, q_blocking = %b", $time, q, q_blocking);
    $finish;
  end
endmodule

from session import run

# Both shift registers on both simulators. Verilator's -Wall reports the blocking assignments; -Wno-fatal lets the
# build go on.
run("""
iverilog -g2012 -Wall -o sim.vvp tb_shift4.sv shift4.sv shift4_blocking.sv
vvp -n sim.vvp
verilator --binary -j 0 -Wall --quiet -Wno-fatal tb_shift4.sv shift4.sv shift4_blocking.sv
obj_dir/Vtb_shift4 +verilator+quiet
""")

# Icarus Verilog 13.0 (stable) · Verilator 5.052
$ iverilog -g2012 -Wall -o sim.vvp tb_shift4.sv shift4.sv shift4_blocking.sv
$ vvp -n sim.vvp
t = 10: q = x, q_blocking = 1
t = 20: q = x, q_blocking = 0
t = 30: q = x, q_blocking = 0
t = 40: q = 1, q_blocking = 0
t = 50: q = 0, q_blocking = 0
tb_shift4.sv:15: $finish called at 50 (1s)
$ verilator --binary -j 0 -Wall --quiet -Wno-fatal tb_shift4.sv shift4.sv shift4_blocking.sv
%Warning-BLKSEQ: shift4_blocking.sv:12:8: Blocking assignment '=' in sequential logic process
                                        : ... note: In instance 'tb_shift4.u_b'
                                        : ... Suggest using delayed assignment '<='
   12 |     s1 = d;
      |        ^
                 ... For warning description see https://verilator.org/warn/BLKSEQ?v=5.052
                 ... Use "/* verilator lint_off BLKSEQ */" and lint_on around source to disable this message.
%Warning-BLKSEQ: shift4_blocking.sv:13:8: Blocking assignment '=' in sequential logic process
                                        : ... note: In instance 'tb_shift4.u_b'
                                        : ... Suggest using delayed assignment '<='
   13 |     s2 = s1;
      |        ^
%Warning-BLKSEQ: shift4_blocking.sv:14:8: Blocking assignment '=' in sequential logic process
                                        : ... note: In instance 'tb_shift4.u_b'
                                        : ... Suggest using delayed assignment '<='
   14 |     s3 = s2;
      |        ^
%Warning-BLKSEQ: shift4_blocking.sv:15:8: Blocking assignment '=' in sequential logic process
                                        : ... note: In instance 'tb_shift4.u_b'
                                        : ... Suggest using delayed assignment '<='
   15 |     q  = s3;
      |        ^
$ obj_dir/Vtb_shift4 +verilator+quiet
t = 10: q = 0, q_blocking = 1
t = 20: q = 0, q_blocking = 0
t = 30: q = 0, q_blocking = 0
t = 40: q = 1, q_blocking = 0
t = 50: q = 0, q_blocking = 0
- tb_shift4.sv:15: Verilog $finish

Read the q column as a waveform. The 1 enters s1 at the edge at 5 and reaches q at the edge at 35, the fourth edge, so q first shows it at t = 40 and drops back to 0 at t = 50. Before that, Icarus Verilog prints x: the stages have no reset, so q holds nothing known until data arrives. Verilator, mostly a two-state simulator, starts them at 0 instead.

Blocking assignments in a clocked block collapse the chain

The q_blocking column shows the 1 at t = 10, after a single edge. With =, s1 = d changes s1 at once, s2 = s1 reads the s1 just written, and so on down the chain, exactly as the traced program’s first half did: every stage holds d after one edge, so only q matters, and q is one flip-flop. Verilator saw it coming, with a BLKSEQ warning for each line, “Blocking assignment ‘=’ in sequential logic process”. Synthesis agrees with the simulation:

from session import run

# What synthesis builds from each shift register: Yosys writes its cell statistics to a file, and grep shows the
# flip-flops.
run("""
yosys -q -p "read_verilog -sv shift4.sv; synth -top shift4; tee -q -o shift4.txt stat"
yosys -q -p "read_verilog -sv shift4_blocking.sv; synth -top shift4_blocking; tee -q -o shift4_blocking.txt stat"
grep DFF shift4.txt shift4_blocking.txt
""")

# Yosys 0.69
$ yosys -q -p "read_verilog -sv shift4.sv; synth -top shift4; tee -q -o shift4.txt stat"
$ yosys -q -p "read_verilog -sv shift4_blocking.sv; synth -top shift4_blocking; tee -q -o shift4_blocking.txt stat"
$ grep DFF shift4.txt shift4_blocking.txt
shift4.txt:        4   $_DFF_P_
shift4_blocking.txt:        1   $_DFF_P_

Four $_DFF_P_ cells, flip-flops on the rising edge, for shift4.sv, and one for shift4_blocking.sv. A design that needed four cycles of delay, to line data up with a slower path, would get one, and everything downstream would be three cycles early. The bug is easy to make because the code looks the same, and the rule that avoids it is short.

A reset either waits for the clock or acts at once

A reset brings registers to a known value. A synchronous resetsynchronous reset: A reset that a flip-flop samples at the clock edge like any other input, so it takes effect only at an edge. is one more input of the flip-flop, sampled at the clock edge: count_sync.sv tests !rst_n inside always_ff @(posedge clk). An asynchronous resetasynchronous reset: A reset that acts as soon as it is asserted, without waiting for a clock edge. In RTL its edge is named in the event control, as in @(posedge clk or negedge rst_n). acts as soon as it is asserted: count_async.sv names the reset’s falling edge in its event control, always_ff @(posedge clk or negedge rst_n), and tests it first, so that the reset’s edge clears the register instead of counting. tb_reset.sv runs both counters and pulls the reset low between two clock edges; $monitor prints a line whenever a value changes, a waveform as text:

// A 4-bit counter with a synchronous, active-low reset: the reset is one more input sampled at the clock edge.
`default_nettype none

module count_sync (
  input  logic       clk,
  input  logic       rst_n,
  output logic [3:0] q
);
  always_ff @(posedge clk) begin
    if (!rst_n) q <= '0;
    else        q <= q + 4'd1;
  end
endmodule

`default_nettype wire

// The same counter with an asynchronous, active-low reset: the falling edge of rst_n wakes the block too.
`default_nettype none

module count_async (
  input  logic       clk,
  input  logic       rst_n,
  output logic [3:0] q
);
  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) q <= '0;
    else        q <= q + 4'd1;
  end
endmodule

`default_nettype wire

// Both counters count from reset; then rst_n falls at 38, between two rising edges, and rises again at 48.
module tb_reset;
  logic       clk, rst_n;
  logic [3:0] q_sync, q_async;

  count_sync  u_sync  (.clk(clk), .rst_n(rst_n), .q(q_sync));
  count_async u_async (.clk(clk), .rst_n(rst_n), .q(q_async));

  initial clk = 1'b0;
  always #5 clk = ~clk;

  initial begin
    rst_n = 1'b0;
    #12 rst_n = 1'b1;
    #26 rst_n = 1'b0;
    #10 rst_n = 1'b1;
    #10 $finish;
  end

  initial $monitor("t = %2d: clk %b rst_n %b | q_sync %2d  q_async %2d", $time, clk, rst_n, q_sync, q_async);
endmodule

from session import run

# $monitor prints a line whenever one of its values changes: a waveform as text.
run("""
iverilog -g2012 -Wall -o sim.vvp tb_reset.sv count_sync.sv count_async.sv
vvp -n sim.vvp
""")

# Icarus Verilog 13.0 (stable)
$ iverilog -g2012 -Wall -o sim.vvp tb_reset.sv count_sync.sv count_async.sv
$ vvp -n sim.vvp
t =  0: clk 0 rst_n 0 | q_sync  x  q_async  0
t =  5: clk 1 rst_n 0 | q_sync  0  q_async  0
t = 10: clk 0 rst_n 0 | q_sync  0  q_async  0
t = 12: clk 0 rst_n 1 | q_sync  0  q_async  0
t = 15: clk 1 rst_n 1 | q_sync  1  q_async  1
t = 20: clk 0 rst_n 1 | q_sync  1  q_async  1
t = 25: clk 1 rst_n 1 | q_sync  2  q_async  2
t = 30: clk 0 rst_n 1 | q_sync  2  q_async  2
t = 35: clk 1 rst_n 1 | q_sync  3  q_async  3
t = 38: clk 1 rst_n 0 | q_sync  3  q_async  0
t = 40: clk 0 rst_n 0 | q_sync  3  q_async  0
t = 45: clk 1 rst_n 0 | q_sync  0  q_async  0
t = 48: clk 1 rst_n 1 | q_sync  0  q_async  0
t = 50: clk 0 rst_n 1 | q_sync  0  q_async  0
t = 55: clk 1 rst_n 1 | q_sync  1  q_async  1
tb_reset.sv:17: $finish called at 58 (1s)

Find the lines at 38 and 45. At 38 the reset falls with no rising clock edge near; q_async drops to 0 on that very line, while q_sync still shows 3 until the edge at 45 samples rst_n and clears it. At the start the same thing happens in miniature: q_async is 0 at time 0, q_sync is x until the first edge at 5. Step through the reset around those lines:

Both styles are in use, and the choice between them, with the timing of a reset’s release, belongs to the reset lesson of the clocks module. Here the point is what each one describes. A start value written in a declaration, such as logic [3:0] q = '0;, is not a reset at all: an FPGA’s bitstream can load it at power-up, but a chip’s flip-flops start in whatever state they settle into, so a design for silicon needs a reset.

An enable becomes a multiplexer in front of the flip-flop

A register that should load only on some edges gets a clock enableclock enable: An input that decides whether a register loads a new value at a clock edge or keeps its value. Synthesis builds it as a multiplexer in front of the flip-flop, or a flip-flop with an enable pin.: if (en) q <= d;. When en is 0 nothing is written at the edge, and in a clocked block that simply means the flip-flop keeps its value; there is no latch, because a flip-flop holds its value between edges anyway. reg_styles.sv writes four 1-bit registers, one in each style, and Yosys reports which flip-flop cell it built for each:

// Four 1-bit registers, one per style: plain, with an enable, with a synchronous reset, with an asynchronous reset.
`default_nettype none

module reg_styles (
  input  logic clk,
  input  logic en,
  input  logic srst_n,  // synchronous reset, active low
  input  logic arst_n,  // asynchronous reset, active low
  input  logic d,
  output logic q_plain,
  output logic q_en,
  output logic q_sync,
  output logic q_async
);
  always_ff @(posedge clk) q_plain <= d;

  always_ff @(posedge clk) begin
    if (en) q_en <= d;
  end

  always_ff @(posedge clk) begin
    if (!srst_n) q_sync <= 1'b0;
    else         q_sync <= d;
  end

  always_ff @(posedge clk or negedge arst_n) begin
    if (!arst_n) q_async <= 1'b0;
    else         q_async <= d;
  end
endmodule

`default_nettype wire

from session import run

# Lint, then the flip-flop cells Yosys picks for each style.
run("""
verilator --lint-only -Wall --quiet reg_styles.sv
yosys -q -p "read_verilog -sv reg_styles.sv; synth -top reg_styles; tee -q -o cells.txt stat"
grep DFF cells.txt
""")

# Verilator 5.052 · Yosys 0.69
$ verilator --lint-only -Wall --quiet reg_styles.sv
$ yosys -q -p "read_verilog -sv reg_styles.sv; synth -top reg_styles; tee -q -o cells.txt stat"
$ grep DFF cells.txt
        1   $_DFFE_PP_
        1   $_DFF_PN0_
        1   $_DFF_P_
        1   $_SDFF_PN0_

The names follow the Yosys cell library, one letter or digit per property:

Yosys used a flip-flop with an enable pin for q_en; where a target has no such cell, the same code becomes a multiplexer that feeds the flip-flop its own output when en is 0. Either way the clock keeps running. Turning the clock itself off, by gating it with logic, saves power but puts logic on the clock path, which brings glitches and timing problems; the clocking lesson of this track covers when and how chips do it safely.

Practise: build a counter in two steps

The lab models a counter’s register in Python, one rising edge per call, in the order of an always_ff block’s tests. The first step adds a synchronous reset, an enable and counting in both directions; the second adds a parallel load with the priorities reset, then load, then enable:

class Counter:
    """A width-bit up/down counter with a synchronous reset and an enable, one rising clock edge at a time."""

    def __init__(self, width):
        self.width = width
        self.value = 0

    def edge(self, rst=0, en=0, up=1):
        """One rising clock edge: rst clears the counter; otherwise en counts up or down, wrapping."""

from counter import Counter


def test_counts_up_when_enabled():
    """counts up by one on every edge with en = 1"""
    c = Counter(4)
    for expected in (1, 2, 3):
        c.edge(en=1)
        assert c.value == expected


def test_holds_without_enable():
    """keeps its value on an edge with en = 0"""
    c = Counter(4)
    c.edge(en=1)
    c.edge(en=0)
    c.edge()
    assert c.value == 1


def test_counts_down_and_wraps():
    """counts down with up = 0, and wraps from 0 to 15"""
    c = Counter(4)
    c.edge(en=1, up=0)
    assert c.value == 15
    c.edge(en=1, up=0)
    assert c.value == 14


def test_wraps_up():
    """wraps from 15 to 0 when counting up"""
    c = Counter(4)
    for _ in range(16):
        c.edge(en=1)
    assert c.value == 0
    c.edge(en=1)
    assert c.value == 1


def test_reset_wins():
    """clears on rst = 1, even when en is 1"""
    c = Counter(4)
    for _ in range(5):
        c.edge(en=1)
    c.edge(rst=1, en=1)
    assert c.value == 0


def test_other_widths():
    """wraps at the counter's own width"""
    c = Counter(3)
    c.edge(en=1, up=0)
    assert c.value == 7
    d = Counter(8)
    d.edge(en=1, up=0)
    assert d.value == 255

class Counter:
    """A width-bit up/down counter with a synchronous reset, a parallel load and an enable."""

    def __init__(self, width):
        self.width = width
        self.value = 0

    def edge(self, rst=0, load=0, d=0, en=0, up=1):
        """One rising clock edge, with the priorities rst, then load, then en."""

from counter import Counter


def test_load_stores_d():
    """stores d on an edge with load = 1"""
    c = Counter(4)
    c.edge(load=1, d=9)
    assert c.value == 9


def test_load_cuts_to_width():
    """keeps only the low bits of a value wider than the counter"""
    c = Counter(4)
    c.edge(load=1, d=20)
    assert c.value == 4


def test_reset_beats_load():
    """clears on rst = 1 even during a load"""
    c = Counter(4)
    c.edge(load=1, d=9)
    c.edge(rst=1, load=1, d=7)
    assert c.value == 0


def test_load_beats_enable():
    """loads instead of counting when load and en are both 1"""
    c = Counter(4)
    c.edge(load=1, d=5, en=1)
    assert c.value == 5


def test_counts_after_load():
    """counts on from a loaded value, and wraps in both directions"""
    c = Counter(4)
    c.edge(load=1, d=15)
    c.edge(en=1)
    assert c.value == 0
    c.edge(en=1, up=0)
    assert c.value == 15
    c.edge(en=1, up=0)
    assert c.value == 14


def test_holds_when_idle():
    """keeps its value with every input at 0"""
    c = Counter(4)
    c.edge(load=1, d=3)
    c.edge()
    assert c.value == 3

Then try the self-check on flip-flops, blocking assignments, resets and enables. It starts each time with the idea you have the fewest right answers on:

Interview questions

Warm-up (fresher): what is the difference between blocking and nonblocking assignments?

A blocking assignment, =, changes its variable at once, so every later statement reads the new value. A nonblocking assignment, <=, reads its right side at once but changes the variable only after every block woken at the same time has run, so they all read the old values. That is what flip-flops clocked by one edge do, so clocked logic uses <=: a chain of registers then behaves as a pipeline, whatever the order of the lines. Combinational logic uses =, so that each line can use the value the line above computed. Mixing them up changes the hardware: four blocking stages of a shift register synthesise to one flip-flop instead of four.

Two harder questions follow, on a reset that must work without a clock and on a pipeline that lost two stages. Plan your answer to each first, then check how your opening compares with the first step:

Key takeaways

• always_ff with nonblocking assignments describes flip-flops that all read their inputs from before the edge, so the 1 of tb_shift4.sv moved one stage per edge and reached q after four.
• The same four lines with blocking assignments copy d through every stage in one edge: one flip-flop instead of four, as Yosys counted, with a BLKSEQ warning from Verilator for each line.
• A synchronous reset waits for the clock, so q_sync kept 3 from 38 to 45, while an asynchronous reset, named in the event control and tested first, cleared q_async at 38.
• A register without a reset shows x on Icarus Verilog and 0 on Verilator, and a start value in a declaration is not a reset on a chip.
• An enable keeps one clock and decides whether to load, which Yosys built as $DFFE_PP; its cell names spell out the clock edge, the enable and the reset of every flip-flop.