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Computer science fundamentals

Digital Design & Verification (Verilog, SystemVerilog, VLSI)

The planned outline of 15 modules. Lessons are reviewed before they are published.

Coming soon 15 modules

Coming soon. This track is being written. Below is its planned outline: a lesson appears here once its examples have been run and its technical review is signed off.

Planned outline

  1. Module 1

    Orientation: chips, roles and the open-source toolchain

    Coming soon
  2. Module 2

    Verilog and SystemVerilog for design: the language core

    Coming soon
  3. Module 3

    Synthesisable RTL style and building blocks

    Coming soon
  4. Module 4

    Finite-state machines in RTL

    Coming soon
  5. Module 5

    Pipelines, handshakes, FIFOs and on-chip buses

    Coming soon
  6. Module 6

    Clocks, resets and clock-domain crossing

    Coming soon
  7. Module 7

    Verification foundations and the SystemVerilog testbench

    Coming soon
  8. Module 8

    Assertions (SVA) and formal verification

    Coming soon
  9. Module 9

    UVM: the Universal Verification Methodology

    Coming soon
  10. Module 10

    Open-source verification in Python: cocotb and pyuvm

    Coming soon
  11. Module 11

    Lint, synthesis, timing, power and test

    Coming soon
  12. Module 12

    The FPGA flow end to end

    Coming soon
  13. Module 13

    The open-source ASIC flow (overview)

    Coming soon
  14. Module 14

    Reading VHDL and other hardware languages

    Coming soon
  15. Module 15

    Interview preparation for design and verification roles

    Coming soon

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