Digital Design & Verification (Verilog, SystemVerilog, VLSI)
Digital Design & Verification (Verilog, SystemVerilog, VLSI) practice
46 exercises and 43 quizzes from the lessons of this track. Sample tests run in your browser; what you pass is kept in this browser only.
Orientation: chips, roles and the open-source toolchain
Verilog and SystemVerilog for design: the language core
- Check an instance's connections before a compiler does
- Quiz: Modules, ports, parameters and hierarchy
- Model indexed part-selects and swap the bytes of a word
- Quiz: Data types, literals and part-selects
- Compare and shift signed and unsigned operands as a simulator does
- Quiz: Operators, expression width and signedness
- Model an 8-input priority encoder with a valid flag
- Model a seven-segment decoder with a default for every other input
- Quiz: Combinational logic with assign and always_comb
- Model an up/down counter with a reset and an enable
- Add a parallel load, with the priorities of an always_ff block
- Quiz: Sequential logic, always_ff and nonblocking
- Find the races between blocks woken by one edge
- Quiz: The event scheduler and race conditions
- Model a barrel shifter built stage by stage
- Quiz: Parameters, generate blocks and packages
- Pack and unpack the fields of an RGB565 struct
- Quiz: Structs, enums, unions and interfaces
- Model a true dual-port RAM with byte enables
- Quiz: Arrays, memories and $readmemh
Synthesisable RTL style and building blocks
- Find where an RTL run and a netlist run part
- Quiz: What synthesis builds, and sim-synth mismatches
- Model the timer in two processes
- Quiz: RTL coding style that scales
- Write the bit-exact model of a fixed-point multiply
- Quiz: Arithmetic datapaths and fixed point
- Model the debouncer and its press detector
- Quiz: Counters, LFSRs, PWM and clock enables
- Model a weighted round-robin arbiter
- Quiz: Muxes, encoders and round-robin arbiters
- Follow an unknown value through a netlist
- Quiz: Gate-level simulation and X-propagation
Finite-state machines in RTL
Pipelines, handshakes, FIFOs and on-chip buses
- Model a pipeline's valid bits with a stall and a flush
- Quiz: Pipelining: latency, throughput and stalls
- Model the skid buffer, edge by edge
- Quiz: Valid/ready handshakes and skid buffers
- Find the smallest FIFO depth that loses no word
- Quiz: Synchronous FIFOs and FIFO depth sizing
- Model the timer's register block
- Quiz: Register blocks: APB, AXI4-Lite and Wishbone
Clocks, resets and clock-domain crossing
- Count the edges of two gated clocks
- Quiz: Clocks for RTL designers: enables, gating, muxes
- Model the reset synchronizer, edge by edge
- Quiz: Reset design and reset synchronizers
- Work out a synchronizer's MTBF in years
- Quiz: Metastability, MTBF and two-flop synchronizers
- Convert Gray code and check a count before it crosses
- Quiz: Multi-bit CDC: handshakes, pulses and Gray code
Lint, synthesis, timing, power and test
- Audit the lint waivers of a file
- Quiz: Linting RTL with Verilator, slang and svlint
- Summarise a Yosys stat report
- Quiz: Logic synthesis with Yosys
- Find the worst setup slack of a timing graph
- Quiz: Static timing analysis fundamentals
- Turn toggle counts into switching power
- Quiz: Low-power RTL techniques and UPF
- Measure the stuck-at fault coverage of a test set
- Quiz: Design for test: scan, ATPG and BIST
The FPGA flow end to end
- Count the block RAMs a memory needs on an iCE40
- Quiz: FPGA architecture for RTL designers
- Find the busiest resource and the timing verdict in a nextpnr report
- Quiz: iCE40 flow: Yosys, nextpnr and IceStorm
- Choose ECP5 PLL dividers the way ecppll does
- Check an LPF file against the ports of a design
- Quiz: ECP5 flow: constraints, PLLs and block RAM
- Decode a UART debug line from samples of the wire
- Quiz: FPGA bring-up and hardware debug
The open-source ASIC flow (overview)
Reading VHDL and other hardware languages
Interview preparation for design and verification roles
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