This page needs a newer browser to run its tools. You can still read everything here.

Digital Design & Verification (Verilog, SystemVerilog, VLSI) Module 14

Reading VHDL and other hardware languages interview questions

Interview questions on reading VHDL and other hardware languages: warm-ups, then what each harder question tests and how a good answer starts.

7 questions: 2 warm-ups and 5 with model answers · Levels: Fresher to staff

Warm-up questions

Short questions with short answers, each answered in full.

Fresher

What is the difference between a signal and a variable in VHDL?

Answered in the lesson Reading VHDL as a Verilog engineer
Mid

What is an embedded HDL, and what does it generate?

Answered in the lesson Chisel, Amaranth, Bluespec and HLS

Questions with model answers

What each question tests, the first step of a good answer and the follow-ups to expect.

Mid to senior

You must integrate a VHDL UART written by another team into a SystemVerilog design whose simulator is Verilator, which reads no VHDL. How do you read the block, show that it does what its documentation says, and get it into the build? Name the tools and the checks.
What it tests

Reading entities, generics and clocked processes, the routes into a Verilog-only flow, and proving a converted or translated block equal to the original by co-simulation on the same stimulus.

First step

Read the entity first: its ports, modes, types and generics are the interface, with every width. Then find each clocked process, its clock and its reset, and note which outputs are 'U' or 'X' before reset. Only then choose how the block reaches Verilator, because each route needs a check that the result still behaves like the VHDL.
Follow-ups
- Which routes into a Verilog-only flow exist with open-source tools, and which would you pick?
- How do you show that the converted or translated block behaves like the original?
- The block's outputs are 'U' until its first clock edge in reset. Does that matter in the SoC?
From the lesson Reading VHDL as a Verilog engineer
Model answer, Pro. Model answers open with any pass; prices are in the notice on this page.
Opening the model answers with your pass…
Model answers open with any MySmartCoPilot pass.
Pro pass · 1 week₹79$2.99
30 days₹179$5.99
1 year₹1,699$45
One payment; a pass never renews. The price shown is the total you pay: no fees or charges are added at checkout.
Passes can’t be bought right now, so the model answers can’t be opened at the moment. If you have a pass, enter your licence key.
Choose a pass I have a licence key
It also opens every other in-depth part in Learn and every Pro tool. Sales are final, except where the law gives you a right to withdraw, for example in the EU and the UK (refund policy).
In the answer:
- Model answer
- Follow-up answers
- Common mistakes
- Rubric
- Variants
- about 3 minutes
Fresher to mid

A VHDL accumulator adds 12-bit unsigned samples into a 16-bit total with acc <= acc + unsigned(sample);. A test of ten small samples passed, but on the board the total wrapped as soon as loud input arrived. Explain what numeric_std did, how you would fix it and what test would have caught it.
What it tests

numeric_std's result widths, unsigned and signed, resize, the number of samples a width can sum, and choosing stimulus that reaches the limits of a datapath.

First step

Work out the widths first. numeric_std's "+" returns as many bits as its longer operand, here the 16 of acc, so the sum is 16 bits and wraps at 65,536 without any message. With samples up to 4,095, that can happen after only 17 samples, so the question is how many samples the total must hold, and the width follows from it.
Follow-ups
- How many samples of 12 bits can a 16-bit total hold in the worst case, and how wide must it be for 1,000,000?
- Why did the short simulation not fail, and which test would fail on the old code?
- What changes if the samples are signed?
From the lesson Reading VHDL as a Verilog engineer
Model answer, Pro.
In the answer:
- Model answer
- Follow-up answers
- Common mistakes
- Rubric
- Variants
- about 3 minutes
Mid to senior

A block written in an embedded HDL fails one test in the SoC simulation. The waveform shows a signal called $27 going wrong one cycle after reset, and the designer who wrote the block has left. How do you find the cause, and what would you put in place so the next failure is quicker to trace?
What it tests

Reading generated Verilog, tracing generated names back to the source, reset and initial values in generated code, and keeping a generated block debuggable by others.

First step

Do not start in the waveform. Open the generated Verilog at the declaration of $27 and follow the generator's own trail back to the source: Amaranth, for example, writes a src attribute naming the Python file and line behind its signals and expressions. Then check how the block resets and what its registers hold before reset, because the failure is one cycle after it.
Follow-ups
- The generated file has no source comments. What then?
- Why look at initial values and reset style first?
- What would you ask every generated block to come with?
From the lesson Chisel, Amaranth, Bluespec and HLS
Model answer, Pro.
In the answer:
- Model answer
- Follow-up answers
- Common mistakes
- Rubric
- Variants
- about 3 minutes
Mid to senior

A 16-tap FIR filter must process 50 million samples a second on a 200 MHz clock. The algorithm exists as a C model. Do you write it in RTL or use high-level synthesis? Size the multipliers and adders either way, and say what you would verify.
What it tests

Turning a throughput target into an initiation interval, unit counts from operations per sample, where HLS fits, and verifying generated RTL against a reference model.

First step

Turn the target into cycles per sample first: 200 MHz divided by 50 million samples a second leaves 4 clock cycles for each sample. Then count what one sample needs, 16 multiplies and 15 additions, and ask how many units must work at once to fit them into those 4 cycles, whichever way the filter is written.
Follow-ups
- What changes if the target rises to 200 million samples a second?
- Which way would you choose, and why?
- How do you verify the result against the C model?
From the lesson Chisel, Amaranth, Bluespec and HLS
Model answer, Pro.
In the answer:
- Model answer
- Follow-up answers
- Common mistakes
- Rubric
- Variants
- about 3 minutes
Senior to staff

Your team of ten writes SystemVerilog and UVM. A new hire proposes moving new blocks to Chisel, and another to Amaranth. How do you decide, what would you try first, and what must stay true of the team's flow whatever language wins?
What it tests

The real gains of embedded HDLs (generation), their costs (a host language, generated names, tooling), keeping the verification flow, and running a measured trial instead of a debate.

First step

Ask what problem the change solves. Embedded HDLs pay off where hardware must be generated in many variants or from computed parameters, not for a fixed block that SystemVerilog parameters cover. Then pick one block where that holds, and measure the trial against its SystemVerilog equivalent.
Follow-ups
- Which block would you choose for the trial?
- What do you measure?
- What must the generated Verilog satisfy before it enters the SoC?
From the lesson Chisel, Amaranth, Bluespec and HLS
Model answer, Pro.
In the answer:
- Model answer
- Follow-up answers
- Common mistakes
- Rubric
- Variants
- about 3 minutes

All Digital Design & Verification (Verilog, SystemVerilog, VLSI) interview questions · The Digital Design & Verification (Verilog, SystemVerilog, VLSI) track

Warm-up questions

What is the difference between a signal and a variable in VHDL?

What is an embedded HDL, and what does it generate?

Questions with model answers

You must integrate a VHDL UART written by another team into a SystemVerilog design whose simulator is Verilator, which reads no VHDL. How do you read the block, show that it does what its documentation says, and get it into the build? Name the tools and the checks.

A VHDL accumulator adds 12-bit unsigned samples into a 16-bit total with acc <= acc + unsigned(sample);. A test of ten small samples passed, but on the board the total wrapped as soon as loud input arrived. Explain what numeric_std did, how you would fix it and what test would have caught it.

A block written in an embedded HDL fails one test in the SoC simulation. The waveform shows a signal called $27 going wrong one cycle after reset, and the designer who wrote the block has left. How do you find the cause, and what would you put in place so the next failure is quicker to trace?

A 16-tap FIR filter must process 50 million samples a second on a 200 MHz clock. The algorithm exists as a C model. Do you write it in RTL or use high-level synthesis? Size the multipliers and adders either way, and say what you would verify.

Your team of ten writes SystemVerilog and UVM. A new hire proposes moving new blocks to Chisel, and another to Amaranth. How do you decide, what would you try first, and what must stay true of the team's flow whatever language wins?