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Digital Design & Verification (Verilog, SystemVerilog, VLSI) Module 11

Lint, synthesis, timing, power and test interview questions

Interview questions on lint, synthesis, timing, power and test: warm-ups, then what each harder question tests and how a good answer starts.

19 questions: 5 warm-ups and 14 with model answers · Levels: Fresher to staff

Warm-up questions

Short questions with short answers, each answered in full.

  1. Fresher

    Why lint RTL when its testbench already passes?

    Answered in the lesson Linting RTL with Verilator, slang and svlint

  2. Fresher

    What does Yosys's proc pass do?

    Answered in the lesson Logic synthesis with Yosys

  3. Fresher

    What is slack in static timing analysis?

    Answered in the lesson Static timing analysis fundamentals

  4. Fresher

    What is the difference between dynamic and leakage power?

    Answered in the lesson Low-power RTL techniques and UPF

  5. Fresher

    What is fault coverage?

    Answered in the lesson Design for test: scan, ATPG and BIST

Questions with model answers

What each question tests, the first step of a good answer and the follow-ups to expect.

  1. Mid to senior

    Your project's lint command has carried -Wno-WIDTHTRUNC for two years, added to quiet a supplied block. A width truncation in new RTL has just reached the lab. What do you change in the flow so that this cannot happen again, without editing the supplied block, and how do you find what else the switch has hidden?

    What it tests
    Scoping waivers to one rule, file and line, Verilator control files, uncovering the backlog a global switch hid, and keeping waivers in the code where every change shows them.
    First step
    Remove the switch in a branch and lint the whole project: every WIDTHTRUNC that appears is either in the supplied block or a finding nobody has seen. Waive the supplied block's lines in a control file read before the sources, with the reason, and sort the rest into fixed, explicitly cast or waived in place with a reason.
    Follow-ups

    From the lesson Linting RTL with Verilator, slang and svlint

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    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 2 minutes

  2. Senior to staff

    Design the lint gate for a team of 40 RTL engineers that uses Verilator, slang and svlint. Which flags does each tool get, where does the gate run, how are waivers controlled, and how do you keep it fast enough to run on every change?

    What it tests
    Exit-status behaviour per tool, warning sets chosen on purpose, local and pull-request runs, a waiver policy with review, and incremental runs that keep the gate fast and trusted.
    First step
    Start from what the gate must decide: a change merges only if every tool ends with status 0. So each tool must fail on what the team forbids: Verilator with -Wall and never -Wno-fatal, slang with the chosen -W groups and -Werror, svlint with a committed rule file. Then put the same script on every computer and in the pull-request job.
    Follow-ups

    From the lesson Linting RTL with Verilator, slang and svlint

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 3 minutes

  3. Fresher to mid

    You synthesise a 20-bit multiply-accumulate unit and the statistics list no cells at all, while synthesis ends with status 0 and prints 16 warnings. Walk through what most likely happened, how you would confirm it, and how your flow should catch it before a netlist leaves synthesis.

    What it tests
    Reading synthesis warnings, how undriven values let optimisation remove logic, checking cell counts against an estimate, and where check -assert must run to be useful.
    First step
    Read the warnings before anything else and compare their number with the widths of the design's signals. Then estimate what the RTL should need, a multiplier and an adder are hundreds of gates, and treat a netlist far below the estimate as lost logic until the log says otherwise.
    Follow-ups

    From the lesson Logic synthesis with Yosys

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 2 minutes

  4. Mid to senior

    A block synthesised to SKY130 standard cells comes out 10 % over its area budget. How do you find where the area goes, what would you try first in the RTL, and how do you know a change helped?

    What it tests
    Reading area per module and per cell type, the sequential share, resource sharing, register widths, and measuring each change on the target library with the same script.
    First step
    Split the area by module and by cell type, flip-flops first, because they are often a large share of a small block. Then look for duplicated arithmetic and registers wider than they need to be, change one thing at a time, and measure each change on the same library and script.
    Follow-ups

    From the lesson Logic synthesis with Yosys

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 2 minutes

  5. Fresher to mid

    The same 8-bit counter synthesises to 22 of Yosys's generic cells, and to other counts on an iCE40 and in a standard-cell library. A manager asks which number to quote for how big the design is. What do you answer, and how would you compare an FPGA cost with a chip cost?

    What it tests
    Understanding what each target's cell is, why counts across targets do not compare, area from a Liberty file, and choosing the measure that fits the question.
    First step
    Say first that a cell means something different on each target: a look-up table, a carry or a flip-flop on an FPGA, one small gate or flip-flop of a library on a chip, and a modelling unit in a generic netlist. Then choose the measure that answers the question asked: area for a chip, device resources for an FPGA.
    Follow-ups

    From the lesson Logic synthesis with Yosys

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 2 minutes

  6. Mid to senior

    After clock tree synthesis, a design that met timing reports a hold violation of 30 ps on a short path between two neighbouring flip-flops, while setup still passes everywhere. Explain how it appeared, whether a slower clock would fix it, and how you would fix it.

    What it tests
    The hold check, skew from a real clock tree, what the clock period does to a hold check, delay insertion on short paths, and checking that the fix does not break setup.
    First step
    Write the hold check with both clock latencies in it, the launch flip-flop's and the capture flip-flop's, and compare the two before and after the clock tree was built. Find the term that moved by 30 ps or more.
    Follow-ups

    From the lesson Static timing analysis fundamentals

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 2 minutes

  7. Mid to senior

    A path has −0.26 ns of setup slack at a 1.6 ns clock, and a second endpoint behind the same adder fails by 0.09 ns. List the fixes you would consider, in the order you would try them, and what each one costs.

    What it tests
    Reading which cells failing paths share, pipelining and its latency, restructuring, sizing, useful skew and its hold cost, and choosing by cost rather than by habit.
    First step
    Find what the two failing paths share: both pass through the adder, so a fix there helps both. Then rank the fixes by what each costs: a register that splits the path costs a cycle of latency, faster logic costs effort or area, skew borrows time from somewhere else, and a slower clock costs the product its speed.
    Follow-ups

    From the lesson Static timing analysis fundamentals

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 2 minutes

  8. Fresher to mid

    A colleague proposes to check timing by running the gate-level netlist with delays through the full regression instead of running static timing analysis. Why is that not enough, and what is gate-level simulation still good for?

    What it tests
    Why STA bounds every path without vectors, why simulation checks only the paths its vectors excite, the cost of each, and what each method checks that the other cannot.
    First step
    A timing simulation finds a slow path only if some vector makes that path switch, and the slowest path may need a rare combination of inputs. STA computes the latest arrival at every node in one sweep over the timing graph, so it bounds every path, whatever the vectors.
    Follow-ups

    From the lesson Static timing analysis fundamentals

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 2 minutes

  9. Mid to senior

    A block of 2,000 flip-flops in groups of 16 is written in 5 % of its cycles and runs at 200 MHz. Estimate what clock gating saves at the clock pins and what it costs, and say when you would not gate a group.

    What it tests
    Per-cycle clock energy of flip-flops and gates from a library, the enabled share, the cost of the gates themselves, break-even group sizes, and the limits of a clock-pin estimate.
    First step
    Work per clock cycle: what a flip-flop's clock pin costs with and without a gate in front of its group, what each gate costs every cycle, and in what share of cycles the groups are written. A cell library's internal-power tables give the energies.
    Follow-ups

    From the lesson Low-power RTL techniques and UPF

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 2 minutes

  10. Mid to senior

    After power gating was added to a DSP block, the always-on logic sometimes reads garbage from the DSP's outputs while the DSP sleeps and for a few cycles after it wakes. What are your hypotheses, and how do you check each?

    What it tests
    Isolation strategies and their clamp values, where isolation controls come from, the order of the power-down and power-up sequence, and checking power intent before simulation.
    First step
    Split the symptom by time: what the outputs do while the DSP sleeps, and what they do in the first cycles after it wakes. For each period, list which part of the power intent and which step of the controller is meant to keep the outputs safe, and check that one first.
    Follow-ups

    From the lesson Low-power RTL techniques and UPF

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 2 minutes

  11. Fresher to mid

    Write the sequence in which a power controller switches a domain with retention registers off and on again, signal by signal, and say what goes wrong when two of its steps change places.

    What it tests
    What the power switch, isolation, retention and the domain's clock each protect, why each step waits for another, and the failures each wrong order causes.
    First step
    List what the controller drives or waits for (the power switch, isolation, save and restore, and the domain's clock), and for each one write what must already be true before it may change. The order follows from those conditions.
    Follow-ups

    From the lesson Low-power RTL techniques and UPF

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 2 minutes

  12. Mid to senior

    A chip ships with 98.5 % stuck-at coverage, and customers return about 1,500 defective parts per million. Explain how that is possible, estimate what higher coverage would gain, and say which tests you would add.

    What it tests
    Relating escapes to yield and coverage, what stuck-at tests miss, at-speed transition tests, and turning a parts-per-million target into a coverage target.
    First step
    Ask what the coverage does not cover: the stuck-at faults the patterns miss, and the defects the stuck-at model cannot see at all. Then relate the share of defective chips that pass the test to the process yield and the coverage with a defect-level model.
    Follow-ups

    From the lesson Design for test: scan, ATPG and BIST

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 2 minutes

  13. Mid to senior

    A chip has 2 million scan flip-flops, needs 12,000 patterns and has 16 pins available for scan. Estimate its scan test time at a 50 MHz shift clock with plain chains, and explain what compression changes.

    What it tests
    The test-time formula, the longest chain as the limit, pins against chains, compression ratios, and the cost of tester time per chip.
    First step
    Work out how many chains the pins allow, one pin in and one out for each, and how long the longest chain is. Then count the shift and capture cycles each pattern needs, add them up over all patterns, and divide by the shift clock.
    Follow-ups

    From the lesson Design for test: scan, ATPG and BIST

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 2 minutes

  14. Fresher to mid

    Plan the memory BIST for a 4,096 x 32 SRAM: which March test you would run, how many operations it takes, which faults it catches, and what the controller must report so that a failing chip can be repaired or analysed.

    What it tests
    March notation and its cost, what MATS+ and March C- detect, data backgrounds for words, failure reporting for repair, and the run time at a given clock.
    First step
    Choose the March test by the faults the memory's technology shows, then count its cost: operations per word times the number of words. Decide also what the controller must keep when a read fails, for repair and for analysis.
    Follow-ups

    From the lesson Design for test: scan, ATPG and BIST

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 2 minutes

All Digital Design & Verification (Verilog, SystemVerilog, VLSI) interview questions · The Digital Design & Verification (Verilog, SystemVerilog, VLSI) track