The 8085 for assembly programmers: a bridge

Add 9AH and 7FH on an 8085 and the sum passes through one register: A, the accumulator, ends with 19H while a one-bit carry flag keeps the ninth bit. Nearly every 8-bit calculation works that way, and that is the first habit a programmer who knows x86-64, AArch64 or RISC-V must change.

Every 8085 program below runs in two simulators, Sim8085 and uCsim. One later part times loops in T-statesT-state: One period of the processor clock, the unit in which Intel's tables time 8085 instructions. How long a T-state lasts depends on the clock a board runs at.. Another corrects binary-coded decimalbinary-coded decimal: A way of storing a decimal number with each digit in its own four bits, so that the byte 58H holds the decimal number 58. Packed BCD keeps two digits in one byte. sums with DAAdecimal adjust: An instruction that turns the binary sum of two packed BCD bytes back into a correct pair of decimal digits. The 8085 calls it DAA and the 8051 DA A.. A third sets a shift-and-add multiply beside RISC-V and raises one of the five interruptsA signal, usually from a device, that makes the processor set the running program aside after its current instruction, run a routine for that device and then carry on with the program..

Arithmetic goes through A; register pairs hold addresses

ADD B means A = A + B; no form adds into C or D. Every 8-bit add, subtract, logical operation and rotate reads and writes A, and a compare subtracts from A, keeping only the flags. Only increments, decrements and the 16-bit DAD do arithmetic in other registers. That makes the 8085 an accumulator machineaccumulator machine: A processor design in which most arithmetic and logic instructions take one operand from a single register, the accumulator, and leave the result there. The 8085 and the 8051 both work this way..

The six others pair up as BC, DE and HL, register pairsregister pair: Two 8-bit registers used together as one 16-bit register for values and memory addresses, such as BC, DE and HL on the 8085. for 16-bit values and addresses, and M is the byte at the address in HL. A 16-bit stack pointerstack pointer: The register that addresses the top of the stack: rsp on x86-64, sp on AArch64 and sp (x2) on RISC-V. Push, pop and function prologues move it; losing it loses the stack. More in “Registers on x86-64, AArch64 and RISC-V” and program counterprogram counter: The register that holds the address of the next instruction a processor will fetch: rip on x86-64, pc on AArch64 and RISC-V. It advances by each instruction's length, and branches, jumps, calls and returns write it. More in “Fetch, decode, execute: the program counter” complete the set. Their nearest matches, from register files and flags and condition codes:

Only IN and OUT reach the 8085’s port-mapped I/Oport-mapped I/O: Device access through a separate address space of I/O ports, which x86 reaches only with the in and out instructions, instead of loads and stores to memory addresses. More in “16-bit x86: real mode and the 8086” space, which x86-64 kept; AArch64 and RISC-V use memory-mapped I/Omemory-mapped I/O: Reaching a device through ordinary loads and stores: the device answers a range of physical addresses, so a store there writes one of its registers instead of RAM. More in “Bare metal: hello from the UART on QEMU”, ordinary loads and stores.

An add writes five flags; DAD writes one, INX none

Five condition flagscondition flags: Single bits that an instruction sets to describe its result: zero, negative, carry and signed overflow. x86-64 keeps them in RFLAGS as ZF, SF, CF and OF, AArch64 in NZCV; RISC-V has none. More in “Flags and condition codes” describe the last result: Z (zero), S (bit 7), P (even parity), the carry flagcarry flag: The flag that records a carry out of the top bit of an addition, which means the unsigned sum did not fit. After a subtraction, x86-64's CF = 1 means a borrow, while AArch64's C = 1 means no borrow. More in “Flags and condition codes” CY (a carry out of bit 7, or a borrow) and AC (a carry out of bit 3). PUSH PSW stores them in one byte, S at bit 7, Z at 6, AC at 4, P at 2 and CY at 0, the layout x86’s LAHF still uses.

flags.asm shows which instructions write them: two adds and two increments, traced in Sim8085 and read back from uCsim:

; Which instructions change the flags: a move, an 8-bit add, a 16-bit add and two increments.
        ORG     0000H
        MVI     A,0FFH      ; A = FFH; a move changes no flag
        ADI     01H         ; A = 00H: Z = 1, CY = 1, AC = 1, P = 1
        LXI     H,1000H     ; HL = 1000H
        LXI     D,0FFFH     ; DE = 0FFFH
        DAD     D           ; HL = 1FFFH: only CY changes, to 0
        INX     H           ; HL = 2000H: no flag changes
        INR     A           ; A = 01H: S, Z, AC and P change, CY does not
        HLT
        END

"""Trace flags.asm in Sim8085, one line per instruction, then read the same registers back from uCsim."""
import pathlib
import sys

sys.path.insert(0, str(pathlib.Path(__file__).parent / "sessions"))
import eightbit

# Two assemblers, then a byte-for-byte comparison of what each HEX file loads.
hexfile = eightbit.asm85("8085/flags.asm")

# Sim8085 prints A and the five flags after every instruction.
eightbit.sim8085(hexfile, "--trace")

# uCsim prints its flag byte (bit 7 S, 6 Z, 4 AC, 2 P, 0 CY) and the register pairs.
eightbit.ucsim85(hexfile, """
run
info registers
""")

$ asl -q -cpu 8085 -L -olist flags.lst -o flags.p 8085/flags.asm
$ p2hex -q flags.p flags.hex
$ sim8085-asm 8085/flags.asm flags-sim.hex
# compare the bytes flags.hex and flags-sim.hex load
same 14 bytes at the same addresses (0000H-000DH)
$ sim8085-run --trace flags.hex
0000 MVI    A,#$ff           A=FF S=0 Z=0 AC=0 P=0 CY=0  T=7
0002 ADI    #$01             A=00 S=0 Z=1 AC=1 P=1 CY=1  T=7
0004 LXI    H,#$1000         A=00 S=0 Z=1 AC=1 P=1 CY=1  T=10
0007 LXI    D,#$0fff         A=00 S=0 Z=1 AC=1 P=1 CY=1  T=10
000a DAD    D                A=00 S=0 Z=1 AC=1 P=1 CY=0  T=10
000b INX    H                A=00 S=0 Z=1 AC=1 P=1 CY=0  T=6
000c INR    A                A=01 S=0 Z=0 AC=0 P=0 CY=0  T=4
000d HLT                     A=01 S=0 Z=0 AC=0 P=0 CY=0  T=5
halted at 000DH after 8 instructions, 59 T-states
A=01 B=00 C=00 D=0F E=FF H=20 L=00 SP=FFFF
flags S=0 Z=0 AC=0 P=0 CY=0
$ ucsim_i8085 -R 1 flags.hex < flags.u85
run
info registers
quit
Simulation started, PC=0x000000
14 words read from flags.hex

Stop at 0x00000e: (101) Halted
F 0x00000e
Simulated 59 ticks (5.900e-05 sec)
SZXA-PVC  Flags= 0x00   0 .  A= 0x01   1 .
00000000
BC= 0xc9c3 [BC]= 0x6c 108 l
DE= 0x0fff [DE]= 0xf4 244 .
HL= 0x2000 [HL]= 0x7a 122 z
SP= 0xdb81 -> 5df1 f095 c436 4738 c025 0897 aa79 12a8 9cda 7e28 988a 091e
0x000e    c9       RET

ADI 01H turned FFH into 00H and set Z, AC, P and CY. DAD D wrote CY alone: 1000H + 0FFFH fits in 16 bits, so CY went to 0 while Z stayed 1. INX H wrote nothing, and INR A rewrote every flag but CY. uCsim agreed on every register the program wrote; its BC = C9C3H is a random start value.

x86-64’s inc also keeps CF, AArch64 sets flags only in instructions such as adds and cmp, and RISC-V has no flags: its branches compare registers.

Four addressing modes, told apart by their bytes

Intel’s manual names four addressing modesThe way an instruction says where its data is: in a register, in the instruction itself, or in memory at an address that the instruction or a register pair gives. for 8085 data. Direct: the instruction’s own bytes 2 and 3 hold the address, low byte first. Register: the instruction names a register or a pair. Register indirect: a pair holds the address. Immediateimmediate: A constant written in an instruction and stored inside its encoding, such as the 5 of mov dword [rbx + 8], 5. AT&T syntax marks it with $ and AArch64 with an optional #, and each instruction set limits which values fit in one instruction. More in “Assembler syntax: NASM, GNU as, Intel and AT&T”: the data is in the instruction. modes.asm adds 9AH and 7FH with all four; step through it:

Both assemblers produced the same 20 bytes; the AS listing spells out each mode:

; Add two bytes with each of the 8085's four data addressing modes; store the sum and the carry.
        ORG     0000H
        LDA     2050H       ; direct: A = the byte at 2050H
        MOV     B,A         ; register: B = A
        LXI     H,2051H     ; immediate: HL = 2051H, the address of the second byte
        MOV     A,M         ; register indirect: A = the byte HL points to
        ADD     B           ; register: A = A + B, CY = carry out of bit 7
        INX     H           ; HL = 2052H; INX changes no flag, so CY survives
        MOV     M,A         ; register indirect: the low byte of the sum
        MVI     A,00H       ; immediate: A = 0
        ACI     00H         ; immediate: A = 0 + 0 + CY
        INX     H           ; HL = 2053H
        MOV     M,A         ; register indirect: the carry, 00H or 01H
        HLT
        ORG     2050H
        DB      9AH, 7FH    ; the two numbers
        END

"""Assemble modes.asm with two assemblers, list its bytes, and run it in both 8085 simulators."""
import pathlib
import sys

sys.path.insert(0, str(pathlib.Path(__file__).parent / "sessions"))
import eightbit

# AS and Sim8085's own assembler, then a byte-for-byte comparison of their HEX files.
hexfile = eightbit.asm85("8085/modes.asm")

# The listing shows each instruction's address and bytes: the length tells the addressing mode.
eightbit.listing("modes.lst")

# The same program in Sim8085's core and in uCsim, with the four bytes at 2050H after the run.
eightbit.sim8085(hexfile, "--dump 2050:4")
eightbit.ucsim85(hexfile, """
run
dump /h rom 0x2050 0x2053
""")

$ asl -q -cpu 8085 -L -olist modes.lst -o modes.p 8085/modes.asm
$ p2hex -q modes.p modes.hex
$ sim8085-asm 8085/modes.asm modes-sim.hex
# compare the bytes modes.hex and modes-sim.hex load
same 20 bytes at the same addresses (0000H-2051H)
# modes.lst: line/address, bytes, source
    1/   0 :                            ; Add two bytes with each of the 8085's four data addressing modes; store the sum and the carry.
    2/   0 :                                    ORG     0000H
    3/   0 : 3A 50 20                           LDA     2050H       ; direct: A = the byte at 2050H
    4/   3 : 47                                 MOV     B,A         ; register: B = A
    5/   4 : 21 51 20                           LXI     H,2051H     ; immediate: HL = 2051H, the address of the second byte
    6/   7 : 7E                                 MOV     A,M         ; register indirect: A = the byte HL points to
    7/   8 : 80                                 ADD     B           ; register: A = A + B, CY = carry out of bit 7
    8/   9 : 23                                 INX     H           ; HL = 2052H; INX changes no flag, so CY survives
    9/   A : 77                                 MOV     M,A         ; register indirect: the low byte of the sum
   10/   B : 3E 00                              MVI     A,00H       ; immediate: A = 0
   11/   D : CE 00                              ACI     00H         ; immediate: A = 0 + 0 + CY
   12/   F : 23                                 INX     H           ; HL = 2053H
   13/  10 : 77                                 MOV     M,A         ; register indirect: the carry, 00H or 01H
   14/  11 : 76                                 HLT
   15/2050 :                                    ORG     2050H
   16/2050 : 9A 7F                              DB      9AH, 7FH    ; the two numbers
   17/2052 :                                    END
$ sim8085-run --dump 2050:4 modes.hex
halted at 0011H after 12 instructions, 83 T-states
A=01 B=9A C=00 D=00 E=00 H=20 L=53 SP=FFFF
flags S=0 Z=0 AC=0 P=0 CY=0
2050: 9A 7F 19 01
$ ucsim_i8085 -R 1 modes.hex < modes.u85
run
dump /h rom 0x2050 0x2053
quit
Simulation started, PC=0x000000
20 words read from modes.hex

Stop at 0x000012: (101) Halted
F 0x000012
Simulated 83 ticks (8.300e-05 sec)
0x2050 9a 7f 19 01 ....

In modes.asm, an instruction’s length gives its mode away. LDA 2050H is three bytes, 3A 50 20. MOV B,A and MOV A,M are one byte each: the registers, or the pair behind M, are coded in the opcode. MVI A,00H and LXI H,2051H carry 8 and 16 bits of data. Both simulators ended with 9A 7F 19 01 at 2050H after 83 T-states; addressing modes shows the forms newer instruction sets add.

Practise

Predict each result, then run a changed copy with the tools of 8-bit toolchains:

1. In modes.asm, change 7FH to 66H. What do 2052H and 2053H hold?
2. In flags.asm, replace INX H with INR L. What do HL and the flags hold after it?
3. Which mode does LDAX D use, and how many bytes is it?

The self-check below asks about the accumulator, the flags and the four modes.

Counting T-states from Intel's timing table Pro: opens with a Pro, Premium or Ultimate pass

DAA, BCD and two flags the simulators disagree on Pro: opens with a Pro, Premium or Ultimate pass

A multiply beside RISC-V, and the five interrupts Pro: opens with a Pro, Premium or Ultimate pass

Interview questions

What makes the 8085 an accumulator machine, and how does that shape a calculation?

Its 8-bit additions, subtractions, logical operations and rotates all read A and leave the result in A; a compare subtracts from A and keeps only the flags. The other registers hold operands and addresses, and apart from increments, decrements and DAD no arithmetic writes them. A calculation becomes a chain: load A, operate, store A, and each partial result must leave A before the next step needs it. RISC-V’s add a2, a0, a1 names any three registers and needs none of those moves.

Three harder questions follow: a delay to size, a flag byte that differs between simulators, and an interrupt that fires once.

Key takeaways

• The 8085 is an accumulator machine: 8-bit arithmetic, logic and rotates read and write A, and only increments, decrements and DAD do arithmetic in other registers.
• BC, DE and HL pair the other registers for 16-bit values and addresses, and M is the byte at the address in HL.
• The five flags sit at bits 7, 6, 4, 2 and 0 of one byte, where x86’s LAHF still puts them; DAD writes only CY and INX writes none.
• An instruction’s length and bytes give its addressing mode away: direct, register, register indirect or immediate.