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GATE CS & DA Preparation Guide Module 5

Digital logic and computer organisation (CS sections 2-3) interview questions

Interview questions on digital logic and computer organisation (CS sections 2-3): warm-ups, then what each harder question tests and how a good answer starts.

20 questions: 5 warm-ups and 15 with model answers · Levels: Fresher to senior

Warm-up questions

Short questions with short answers, each answered in full.

  1. Fresher

    What is the difference between a prime implicant and an essential prime implicant?

    Answered in the lesson Boolean minimisation: K-maps and the tabular method

  2. Fresher

    Why do computers store signed integers in two's complement rather than in sign-magnitude?

    Answered in the lesson Circuit design, number systems and IEEE 754

  3. Fresher

    What is an effective address, and how many memory reads do direct and indirect addressing need for their operand?

    Answered in the lesson Instruction sets, addressing modes, ALU and control

  4. Fresher

    What is locality of reference, and why does it let a small cache serve most memory accesses?

    Answered in the lesson Memory hierarchy, interfacing and cache mapping

  5. Fresher

    Why is the speedup of a k-stage pipeline less than k in practice?

    Answered in the lesson Pipelining, hazards, interrupts and DMA

Questions with model answers

What each question tests, the first step of a good answer and the follow-ups to expect.

  1. Fresher to mid

    A classmate's K-map program always circles the largest remaining group first. It passes every textbook example you try, then gives five terms where four are enough. What kind of function breaks it, and how would you change the algorithm so that it is always right?

    What it tests
    Understanding prime and essential prime implicants, why largest-first is a heuristic, and turning the chart procedure into a correct algorithm.
    First step
    Separate finding the groups from choosing them, and recall which groups every minimal cover must contain. Then ask whether the largest group on a map is always one of those.
    Follow-ups

    From the lesson Boolean minimisation: K-maps and the tabular method

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    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 3 minutes

  2. Fresher to mid

    For a function with don't-cares, your minimal sum of products and your minimal product of sums give different outputs on one input. A friend says one of them must be wrong. Is that true? Explain, and say how you would check both answers.

    What it tests
    What a don't-care means, how SOP and POS minimisation each use them, and checking an answer against the specified rows only.
    First step
    Recall what a don't-care promises: the input never occurs, or its output does not matter. Then ask whether the two expressions must agree on such an input for both to be correct.
    Follow-ups

    From the lesson Boolean minimisation: K-maps and the tabular method

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 2 minutes

  3. Fresher

    A numerical answer question asks for the number of essential prime implicants of a four-variable function with two don't-cares. How do you get an exact count in about three minutes, and where do most candidates lose the mark?

    What it tests
    A reliable order of work on a K-map, the definitions of prime and essential prime implicants, and the role of don't-cares in the chart.
    First step
    Draw the map with the don't-cares, list every prime implicant before choosing anything, and only then look at each 1 to see how many of the listed groups cover it.
    Follow-ups

    From the lesson Boolean minimisation: K-maps and the tabular method

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 2 minutes

  4. Fresher to mid

    An 8-bit ALU sets its signed overflow flag from the carry out of the most significant bit. Which additions does it get wrong, roughly how many of the 65,536 possible ones, and how should the flag be computed?

    What it tests
    The difference between unsigned carry and signed overflow, the carry-in versus carry-out rule, and checking a design rule exhaustively.
    First step
    Write down when a signed 8-bit sum really overflows: only when both operands have the same sign and the true sum leaves −128 to 127. Then compare that with when the carry out of bit 7 is 1, starting with −1 + 1.
    Follow-ups

    From the lesson Circuit design, number systems and IEEE 754

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 2 minutes

  5. Fresher to mid

    A program adds 0.1 to a single-precision total ten times and then tests whether the total equals 1.0. The test fails. Explain why, bit by bit, and say how you would compare floating-point results instead.

    What it tests
    How decimal fractions are stored in binary, rounding at every operation, the size of one unit in the last place, and tolerant comparison.
    First step
    Start with what is actually stored for 0.1: its binary expansion repeats, so single precision keeps the nearest value with a 24-bit significand, which is not exactly 0.1. Then follow what each addition does to the total.
    Follow-ups

    From the lesson Circuit design, number systems and IEEE 754

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 2 minutes

  6. Fresher to mid

    You designed a mod-6 counter on three flip-flops, treating the two unused states as don't-cares. On some boards it sometimes never starts counting after power-on. What could have happened, and how do you change the design so it cannot?

    What it tests
    The meaning of don't-cares in state machines, analysing unused states, lock-out, and designing for a known start state.
    First step
    List the two unused states and work out where your next-state equations send each of them. Ask whether every unused state reaches the counting sequence, and what the flip-flops hold right after power-on.
    Follow-ups

    From the lesson Circuit design, number systems and IEEE 754

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 2 minutes

  7. Fresher to mid

    A branch at byte address 2,000 on a machine with 4-byte instructions has the offset −12. Your friend says the target is 1,988 and you say 1,992. Who is right, what decides it, and what other answer could a third convention give?

    What it tests
    Reading PC-relative conventions precisely: which PC the offset is added to, and whether the offset counts bytes or instructions.
    First step
    Write down the two candidate bases: the address of the branch itself and the updated PC, the address of the next instruction. Then ask whether the offset counts bytes or whole instructions.
    Follow-ups

    From the lesson Instruction sets, addressing modes, ALU and control

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 2 minutes

  8. Fresher to mid

    A 16-bit instruction format has 4-bit register fields. It must hold 12 three-register instructions and at least 100 one-register instructions, and as many two-register instructions as possible. How many two-register instructions fit, and how much room is left for zero-register ones?

    What it tests
    Expanding opcodes: counting escape values, capacity per format, and planning the formats in the right order.
    First step
    Lay out each format's opcode width: 4 bits with three register fields, 8 bits with two, 12 with one and 16 with none. Count how many 4-bit values the three-register instructions leave as escapes, and what each escape opens in the next format.
    Follow-ups

    From the lesson Instruction sets, addressing modes, ALU and control

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 2 minutes

  9. Fresher to mid

    You design the control unit of an 8-bit teaching processor with 40 instructions, and every year students will add new instructions to it. Would you build hardwired or microprogrammed control? Justify the choice with the costs you would estimate.

    What it tests
    The speed and flexibility trade-off between the two kinds of control, estimating control-memory size, and matching a design to how it will change.
    First step
    Start from the requirement that matters most here: instructions change every year. Then estimate what each design costs in speed, in memory and in the work of adding one instruction.
    Follow-ups

    From the lesson Instruction sets, addressing modes, ALU and control

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 2 minutes

  10. Fresher to mid

    For a 32-bit processor you must choose a 32 KiB cache with 64-byte blocks, either direct-mapped or 4-way set-associative. Compare their tag storage and lookup hardware with numbers, and say which suits a loop that alternates between two arrays placed exactly 32 KiB apart.

    What it tests
    Address splitting, tag-directory sizing, the cost of associativity, and recognising conflict misses from an address pattern.
    First step
    Split the address for both caches: 512 lines, a 6-bit offset, and the index and tag that follow from the number of sets. Then work out which lines two addresses exactly one cache size apart map to.
    Follow-ups

    From the lesson Memory hierarchy, interfacing and cache mapping

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 2 minutes

  11. Fresher to mid

    A routine over a 64 × 64 array of 4-byte integers becomes eight times slower after a colleague swaps its two loops. With a 4 KiB direct-mapped cache and 32-byte blocks, explain the slowdown with miss counts, and give two fixes other than swapping the loops back.

    What it tests
    Row-major layout, spatial locality, conflict misses from a power-of-two stride, and loop and data transformations.
    First step
    Work out how far apart in memory two consecutive accesses are in each loop order, and how many integers one block holds. Then find which cache lines the elements of one column map to.
    Follow-ups

    From the lesson Memory hierarchy, interfacing and cache mapping

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 3 minutes

  12. Mid to senior

    A logging service appends 100 MB of records per second and almost never reads them back. Would you want its stores to go through a write-back, write-allocate cache, or to bypass the cache? Estimate the memory traffic of each choice.

    What it tests
    Write policies and write-allocate, traffic estimates, cache pollution, and when streaming stores pay off.
    First step
    Follow one 64-byte block of log through each policy: what is read from memory on the first write, what is written when, and what else the block pushes out of the cache.
    Follow-ups

    From the lesson Memory hierarchy, interfacing and cache mapping

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 2 minutes

  13. Fresher to mid

    On a 5-stage pipeline, how many cycles does LW R1,0(R9); ADD R2,R1,R3; LW R4,8(R9); SUB R5,R4,R2; OR R6,R5,R1 take without forwarding and with full forwarding? Say which values are forwarded and which stalls remain.

    What it tests
    Finding RAW dependences, applying the stall rules with and without forwarding, and drawing or reasoning through a space-time diagram.
    First step
    List each instruction's sources and the instruction that last wrote each one, with the distance between them. Then state when your pipeline writes and reads the register file, because the stall counts depend on it.
    Follow-ups

    From the lesson Pipelining, hazards, interrupts and DMA

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 3 minutes

  14. Mid to senior

    Your 5-stage pipeline decides branches in EX. 18 % of instructions are branches and 70 % of those are taken. Would you move the branch decision to ID, or keep it in EX and add a predictor that is right 90 % of the time? Compare the CPIs and the hidden costs.

    What it tests
    Branch penalties, the effect of prediction accuracy, and the clock-period cost of moving work into an earlier stage.
    First step
    Write the penalty of each option in cycles per branch, and say what each needs to fetch the right instruction early: a comparator and an adder in ID, or a predictor that also knows the target address at fetch.
    Follow-ups

    From the lesson Pipelining, hazards, interrupts and DMA

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 2 minutes

  15. Fresher to mid

    A sensor delivers 2-byte samples, 250,000 a second, to a microcontroller whose interrupt handler takes 6 µs. Would you use one interrupt per sample, a 32-sample buffer with one interrupt per batch, or DMA? Show the processor time each one costs.

    What it tests
    Turning a device rate and overheads into processor and bus shares, and matching the input method to the rate.
    First step
    Find the time between samples first. Then compare it with the handler's 6 µs for one interrupt per sample, and work out how the share changes when one interrupt serves many samples.
    Follow-ups

    From the lesson Pipelining, hazards, interrupts and DMA

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 2 minutes

All GATE CS & DA Preparation Guide interview questions · The GATE CS & DA Preparation Guide track