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C++ Module 21

Embedded C++ interview questions

31 interview questions on embedded C++ from C++: short warm-ups, then what each harder question tests, the first step of a good answer and its follow-ups.

31 questions: 8 warm-ups and 23 with model answers · Levels: Fresher to staff

Warm-up questions

Short questions with short answers, each answered in full.

  1. Fresher to mid

    What is the difference between a hosted and a freestanding C++ implementation, and which one does Cortex-M firmware use?

    Answered in the lesson Embedded C++: freestanding, no exceptions, no heap

  2. Fresher to mid

    What do the three parts of arm-none-eabi mean, and why can the program it builds not run on the laptop that built it?

    Answered in the lesson Cross-compiling for Arm Cortex-M and running in QEMU

  3. Fresher to mid

    What does volatile guarantee for an access to a memory-mapped register, and what does it not guarantee?

    Answered in the lesson Memory-mapped registers and volatile in C++

  4. Fresher to mid

    What should an interrupt handler avoid doing, and why?

    Answered in the lesson Interrupt-safe ring buffers in embedded C++

  5. Fresher to mid

    What do Q15 and Q16.16 mean, and what range and step does each give?

    Answered in the lesson Fixed-point arithmetic in C++ firmware

  6. Fresher to mid

    Why should a firmware state machine handle every event in every state, even the events it ignores?

    Answered in the lesson State machines for firmware in C++

  7. Fresher to mid

    What is a hardware abstraction layer, and why does it make firmware testable on a laptop?

    Answered in the lesson Testing firmware logic on your laptop

  8. Fresher to mid

    What does a coding guideline set such as MISRA C++:2023 try to prevent, and why are tests alone not enough?

    Answered in the lesson Safety-critical C++ and MISRA C++:2023

Questions with model answers

What each question tests, the first step of a good answer and the follow-ups to expect.

  1. Mid to senior

    A Cortex-M4 firmware must fit in 256 KB of flash. The first build, which parses its configuration with std::stoi, std::vector and exceptions and logs through iostream, fails to link because the flash region overflows. How do you find what is taking the space, and what do you change?

    What it tests
    Reading linker errors, size reports and symbol sizes, the costs of iostream, exceptions and their terminate handler, and replacing them with fixed-capacity code that reports errors as values.
    First step
    Do not guess. Link once against a temporarily larger region, or read the linker map, and list the largest symbols with nm --size-sort. Then group them by what pulled them in: iostream's locales and streams, the exception runtime and its terminate handler, printf's formatting engine, and the heap.
    Follow-ups

    From the lesson Embedded C++: freestanding, no exceptions, no heap

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    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 3 minutes

  2. Mid to senior

    Your firmware is built with -fno-exceptions. How should a sensor driver report that the sensor did not answer, and what happens to standard library calls that would normally throw, such as std::vector::at or std::optional::value?

    What it tests
    Error handling without exceptions with std::expected, std::optional and error codes, what libstdc++ does at throw sites, and C++26's freestanding-deleted functions.
    First step
    Separate expected failures from bugs. A sensor that does not answer is an expected failure, so it belongs in the return type, for example std::expected<Reading, SensorError>. A broken invariant is a bug, which should stop the program in a defined way rather than travel up as a value.
    Follow-ups

    From the lesson Embedded C++: freestanding, no exceptions, no heap

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 3 minutes

  3. Mid to senior

    A global int threshold = 25; reads as 0 on the board, while a host build of the same code prints 25. The firmware has its own linker script and start-up code. What do you check, and in what order?

    What it tests
    Load and run addresses of .data, copying .data and zeroing .bss in start-up code, the linker-script symbols they use, and reading the map file or ELF headers.
    First step
    Ask where the 25 is before main runs, and what puts it into RAM: on the board nothing does unless the start-up code does. Check that code, and the linker-script symbols it relies on, before you suspect the C++.
    Follow-ups

    From the lesson Cross-compiling for Arm Cortex-M and running in QEMU

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 3 minutes

  4. Senior to staff

    Your team wants to run firmware tests in QEMU on the build server instead of on boards. What can QEMU tell you reliably, what can it not, and how would you design the test setup?

    What it tests
    What emulation models and does not model, semihosting for test output and exit codes, determinism with icount, and a test pyramid across host, emulator and hardware.
    First step
    Sort the risks before choosing tools: list what can go wrong with the firmware, from its logic and its start-up code to timing, peripherals and the chip's errata, and for each ask whether an emulator models it at all. Then decide what each layer proves and how a test reports its result from inside QEMU.
    Follow-ups

    From the lesson Cross-compiling for Arm Cortex-M and running in QEMU

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 3 minutes

  5. Mid to senior

    Debug builds at -O0 no longer fit in flash, and one module behaves differently between the debug build and the -Os release build. How do you approach the two problems?

    What it tests
    Size differences between optimisation levels, -Og, section garbage collection, and why optimisation exposes undefined behaviour, missing volatile or races with interrupts.
    First step
    Treat them separately. For size, measure before you change a flag: compare the two size reports and the largest symbols. For the behaviour difference, suspect code whose meaning depends on the optimiser: undefined behaviour, a register accessed without volatile, or data shared with an interrupt without atomics.
    Follow-ups

    From the lesson Cross-compiling for Arm Cortex-M and running in QEMU

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 3 minutes

  6. Fresher to mid

    A loop that polls a status register works at -O0 and hangs at -O2 on the board. The register is read through a plain std::uint32_t pointer. Explain what the optimiser did, how you would prove it, and how you fix it.

    What it tests
    The as-if rule and observable behaviour, why plain loads may be hoisted out of a loop, reading disassembly, and the correct use of volatile for registers.
    First step
    Ask what the compiler may assume about a plain object: nothing in the loop writes it, so its value cannot change, and one load before the loop, or none, is as good as one per pass. Then confirm it in the disassembly of the loop rather than by trying flags.
    Follow-ups

    From the lesson Memory-mapped registers and volatile in C++

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 3 minutes

  7. Mid to senior

    A driver maps a peripheral's control register as a struct of volatile bit-fields and sets several fields one after another. What can go wrong, on Arm and elsewhere, and what do you propose instead?

    What it tests
    Implementation-defined bit-field layout, the AAPCS rules for volatile bit-field accesses, hidden reads of registers with side effects, write-one-to-clear flags, and alternatives with masks or typed fields.
    First step
    Count the bus accesses each line of the driver makes, and check them against what the target's ABI says a write to a volatile bit-field does. Then look for registers where a read, or writing back what was read, has a side effect the peripheral notices.
    Follow-ups

    From the lesson Memory-mapped registers and volatile in C++

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 3 minutes

  8. Senior to staff

    Design a type-safe register access layer in C++ for a team's drivers: fields with access rights, combined writes, read-modify-write, and tests on the host. What does it cost at run time, and how do you show that?

    What it tests
    Templates and constraints for register descriptions, compile-time rejection of misuse, zero-cost abstraction checked in the disassembly, a bus abstraction for host tests, and generation from vendor descriptions.
    First step
    Start from what drivers do with registers: read one field, set several fields at once, change one field and keep the others, and what each of these must never do to the hardware. Then decide how to describe registers and fields so that the compiler checks those rules, and how a test can stand in for the hardware.
    Follow-ups

    From the lesson Memory-mapped registers and volatile in C++

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 3 minutes

  9. Mid to senior

    An interrupt handler and the main loop both increment a shared volatile counter, and at the end of a test the total is lower than the number of increments. Explain why, estimate how many are lost, and give two fixes with their costs.

    What it tests
    Read-modify-write races with an interrupt, why volatile does not make them atomic, estimating losses from the instruction window, and critical sections against atomic operations.
    First step
    Write out main's increment as instructions: a load, an add and a store, with the loop's own instructions around them. An interrupt that arrives between the load and the store updates the counter, then main stores a value computed from the old one. The share of instruction boundaries inside that window predicts the share lost.
    Follow-ups

    From the lesson Interrupt-safe ring buffers in embedded C++

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 3 minutes

  10. Mid to senior

    Design the buffer between a UART receive interrupt and the main loop. Bytes arrive at 115,200 baud, and the main loop sometimes stalls for 20 ms while it writes to flash. What size, which indices and memory orders, and what happens when it is full?

    What it tests
    Sizing from the arrival rate and the longest stall, single-producer single-consumer design with release and acquire, power-of-two capacity, the full policy, and how to test it.
    First step
    Work out the arrival rate: with 8 data bits, no parity and one stop bit, each byte takes 10 bit times, so 115,200 baud delivers 11,520 bytes a second. A 20 ms stall therefore lets about 230 bytes arrive, which sets the minimum capacity before any margin.
    Follow-ups

    From the lesson Interrupt-safe ring buffers in embedded C++

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 3 minutes

  11. Senior to staff

    Code that calls fetch_add on a std::atomic<std::uint32_t> compiles and links for a Cortex-M4 but fails to link for a Cortex-M0+ with an undefined __atomic_fetch_add_4. Why, and what are your options?

    What it tests
    Instruction-set support for atomic read-modify-write, is_always_lock_free, compiler library calls for atomics, critical sections on a single core, and designs that need no read-modify-write.
    First step
    Start from the missing symbol: __atomic_fetch_add_4 is a function the compiler calls when it cannot build the operation from instructions. Compare what the Cortex-M0+ and the Cortex-M4 offer for an atomic read-modify-write, and what std::atomic<std::uint32_t>::is_always_lock_free says on each.
    Follow-ups

    From the lesson Interrupt-safe ring buffers in embedded C++

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 3 minutes

  12. Mid to senior

    A Q16.16 low-pass filter, y += alpha * (x - y) with alpha = 0.01, runs on a Cortex-M0. With a constant input of 2.5 it settles 100 steps of 1/65,536 below 2.5 and never gets closer. Explain why, and fix it.

    What it tests
    Fixed-point rounding, the dead band of recursive filters, and fixes that keep precision without a floating-point unit or expensive arithmetic.
    First step
    Write the update in raw integers: the increment is alpha's raw value times the difference x − y, shifted right by 16. Find the largest difference for which that increment is zero; once the output is that close, it cannot move.
    Follow-ups

    From the lesson Fixed-point arithmetic in C++ firmware

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 3 minutes

  13. Senior to staff

    You are porting a PID control loop from float on a PC to a Cortex-M0 without a floating-point unit. How do you choose a fixed-point format for each variable, and how do you show that the port is accurate enough?

    What it tests
    Range and resolution analysis, headroom for products and sums, per-variable scaling, the cost of operations on a small core, and verifying a port against a floating-point reference.
    First step
    List every variable with its physical range and the smallest change that matters, taken from the sensor, actuator and control specifications. The range sets the integer bits, the resolution sets the fraction bits, and every product and sum needs its own headroom.
    Follow-ups

    From the lesson Fixed-point arithmetic in C++ firmware

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 3 minutes

  14. Mid to senior

    A golden-output test compares 1,000 outputs of a float filter bit for bit. It passes on developers' machines and fails on the CI server, which builds the same code with GCC at -O2 for the same processor. What is the likely cause, and what do you change?

    What it tests
    Floating-point contraction and other build-dependent rounding, deterministic testing strategies, and when fixed point is the right fix rather than a looser test.
    First step
    Compare the two builds' compiler and flags before suspecting the code. The optimisation level and the contraction setting decide whether a multiplication and an addition become one fused instruction, which changes the last bit of some results.
    Follow-ups

    From the lesson Fixed-point arithmetic in C++ firmware

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 3 minutes

  15. Mid to senior

    An interrupt handler calls the door controller's dispatch() when the motor reaches its end stop, and the main loop calls dispatch() for keypad events. About once a week a unit ends up in the wrong state. What do you suspect, and how do you restructure the code?

    What it tests
    Re-entrancy and run-to-completion, data races between an interrupt and the main loop, event queues, and making a rare failure reproducible.
    First step
    Notice that dispatch() has two callers that can interrupt each other. If the interrupt arrives while the main loop is halfway through a transition, the inner call sees a half-updated state, and the outer call then overwrites what the inner call did.
    Follow-ups

    From the lesson State machines for firmware in C++

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 3 minutes

  16. Senior to staff

    A battery charger controller has 12 states and 15 events, and two states must remember data: a charge timer and a fault code. Your team argues between a switch, a transition table and std::variant on a Cortex-M0+ with 32 KB of flash. How do you decide?

    What it tests
    Weighing reviewability, compile-time checks, data that belongs to one state and code size, measuring instead of assuming, and keeping the tests independent of the form chosen.
    First step
    Write down what the code must make hard to get wrong: forgotten events, conflicting transitions, data used in the wrong state. Then measure each candidate's flash cost with the real compiler and flags, because on a small part the cheapest form to read is not always the cheapest to store.
    Follow-ups

    From the lesson State machines for firmware in C++

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 3 minutes

  17. Mid to senior

    How do you test a state machine with 8 states and 10 events so that you know every transition is covered, and what can such tests still miss?

    What it tests
    Exhaustive testing of state and event pairs, reaching states deliberately, specification tables as the oracle, random walks with invariants, and the limits of tests that feed events by hand.
    First step
    Count the pairs: 8 states times 10 events are 80 cells, each with an expected next state from the specification. A test that drives the machine into every state and sends every event checks all 80 directly.
    Follow-ups

    From the lesson State machines for firmware in C++

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 3 minutes

  18. Mid to senior

    Your driver's unit tests pass on every developer's laptop, but on the device the same code reports −40 °C as 216 °C. What could make the host and the target disagree, and how do you catch such bugs before flashing?

    What it tests
    Knowing the ABI differences between a computer and a microcontroller, reasoning from a symptom to a type, and running tests under the target's rules.
    First step
    Look at the numbers: 216 is 256 − 40, so a byte that should be negative is read as unsigned. Find where the driver turns a register byte into a signed value, and ask whether that step depends on how plain char is defined.
    Follow-ups

    From the lesson Testing firmware logic on your laptop

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 3 minutes

  19. Senior to staff

    A team writes 40 drivers for a Cortex-M0+ with 32 KB of flash and wants every driver testable on the host. Should the hardware access be injected with templates or with virtual interfaces?

    What it tests
    Measuring the cost of indirection and inlining on a small core, code duplication from templates, build structure, and the kinds of test double each choice allows.
    First step
    Measure before deciding: build one driver both ways with the real compiler and flags, compare the size and the calls in the generated code, then scale by 40 drivers and by the number of bus types each driver must work with.
    Follow-ups

    From the lesson Testing firmware logic on your laptop

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 3 minutes

  20. Senior to staff

    Which parts of a firmware can host tests not be trusted with, and what does your test strategy look like from a commit to a release?

    What it tests
    Knowing what host tests and emulators can and cannot show, layering tests by cost, and turning hardware-only risks into targeted tests on real boards.
    First step
    List the risks by where they live: logic and decoding, which host tests cover; types, the ABI and the compiler's code, which an emulator covers; and timing, interrupts and peripherals, which only real hardware shows.
    Follow-ups

    From the lesson Testing firmware logic on your laptop

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 3 minutes

  21. Senior to staff

    Your product must follow MISRA C++:2023, but a third-party communication library you need uses exceptions, dynamic memory and recursion. What do you do?

    What it tests
    Handling adopted code under a guideline set: isolation, deviations for adopted code, wrappers, evidence, and the trade-off against replacing the library.
    First step
    Treat it as adopted code, not as your own: MISRA Compliance expects adopted code to be identified and its violations justified on that basis. Then decide where the library may run and how its failures are contained.
    Follow-ups

    From the lesson Safety-critical C++ and MISRA C++:2023

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 3 minutes

  22. Senior to staff

    An analyser reports 3,000 guideline findings on an existing 80,000-line code base that must now comply. How do you plan the work?

    What it tests
    Triage by category and risk, baselining, gates on new code, re-categorisation, deviations, and measuring progress without gaming the count.
    First step
    Do not start fixing in file order. Freeze a baseline, stop new violations with a gate on changed lines, then sort the 3,000 by guideline category and by what the code does, so that mandatory rules and safety-relevant modules come first.
    Follow-ups

    From the lesson Safety-critical C++ and MISRA C++:2023

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 3 minutes

  23. Mid to senior

    Does adopting C++26 contracts and a hardened standard library make a guideline set such as MISRA C++:2023 unnecessary?

    What it tests
    Run-time checks against prevention, evaluation semantics, what certification needs as evidence, and how the two approaches combine.
    First step
    Separate when each acts: contracts and hardening check conditions while the program runs and stop or report a violation; guidelines and analysers aim to keep the violation from being written at all. A safety argument needs both.
    Follow-ups

    From the lesson Safety-critical C++ and MISRA C++:2023

    In the answer:

    • Model answer
    • Follow-up answers
    • Common mistakes
    • Rubric
    • Variants
    • about 3 minutes

All C++ interview questions · The C++ track