Comparing x86-64, AArch64 and RISC-V

Compiled by one compiler for size, five small C functions take 127 bytes of x86-64 code, 176 of AArch64 code and 122 of RISC-V code, or 188 when RISC-V leaves out its compressed instructions. Comparing x86-64 with the two load/store ISAs on measured code beats any slogan: what decides is which operations each encoding makes short.

This page compares the three ISAs in one table and measures those five functions on four targets. Three further parts show what modelled cores make of an instruction count, write one base64 encoder by hand for each ISA, and port C between the ISAs.

Seven rows hold the differences you meet first

Each of the three is an instruction set architectureinstruction set architecture: The contract between software and a processor: the registers a program may name, the instructions that act on them, how those instructions are encoded as bytes and the rules for memory, interrupts and privilege. x86-64, AArch64 and RISC-V are three ISAs. More in “What assembly language is and why it matters”, a contract for registers, instructions, their bytes and memory. Comparing x86-64, AArch64 and RISC-V row by row shows where the contracts differ:

x86-64 lets most arithmetic read or write memory and packs it into variable-length encodingsvariable-length encoding: An instruction encoding in which an instruction's size depends on what it does. x86-64 instructions are 1 to 15 bytes of optional prefixes, opcode, ModRM, SIB, displacement and immediate, which packs code densely but complicates decoding. More in “Instruction encoding: fixed and variable”. It sets its condition flagscondition flags: Single bits that an instruction sets to describe its result: zero, negative, carry and signed overflow. x86-64 keeps them in RFLAGS as ZF, SF, CF and OF, AArch64 in NZCV; RISC-V has none. More in “Flags and condition codes” as a side effect of almost every add and compare. AArch64 is a load/store architectureload/store architecture: An instruction set in which only load and store instructions access memory and every arithmetic or logic instruction works on registers alone. AArch64 and RISC-V are load/store; x86-64 is not, because many of its instructions take a memory operand. More in “Loads and stores of every width” with a fixed 4-byte encoding. Its NZCV flags change only when an instruction such as cmp asks. RISC-V is load/store too and has no flags: blt a0, a1, label compares two registers itself. Its C extension adds compressed instructionscompressed instructions: Two-byte encodings of common RISC-V instructions, defined by the C extension. Each one expands to a single standard 4-byte instruction, so the same program takes less space; a core must implement C to run them. More in “Compiler idioms you will meet”, 2-byte forms of the commonest ones.

Five everyday operations show the rows at work:

The division and system-call rows change behaviour after a port. Division runs all three division-by-zero cases, and Linux system calls shows why AArch64 and RISC-V share one table of system-call numberssystem-call number: The number a program loads into a register (rax, x8 or a7 on Linux) to say which system call it wants. Numbers come from a per-architecture table, so write is 1 on x86-64 and 64 on AArch64. More in “Linux system calls on three ISAs”. Under total store order, other cores see a core’s stores in program order. The weak models keep that order only where code asks, as memory ordering shows.

Code size follows the encodings, not the CISC or RISC label

The usual story says a CISCCISC: Complex instruction set computer: a label for ISAs such as x86-64 whose instructions vary in length and whose arithmetic instructions can read or write memory directly. instruction set gives smaller programs than a RISCRISC: Reduced instruction set computer: a label for load/store ISAs such as AArch64 and RISC-V, whose regular instructions touch memory only through loads and stores. one because each instruction does more. five.c tests it with five functions that stress different parts of an encoding: a division loop, two comparisons, a byte loop, two 64-bit constants and two counters in memory.

/* five.c: five small functions, compiled for four targets. */
#include <stddef.h>
#include <stdint.h>

/* Euclid's algorithm: a loop around one division. */
uint64_t gcd(uint64_t a, uint64_t b) {
    while (b != 0) {
        uint64_t r = a % b;
        a = b;
        b = r;
    }
    return a;
}

/* Two comparisons and no loop. */
int clamp(int x, int lo, int hi) {
    if (x < lo) return lo;
    if (x > hi) return hi;
    return x;
}

/* A byte loop that stops at the first byte that is not a space. */
size_t skip_spaces(const char *s) {
    size_t n = 0;
    while (s[n] == ' ') n++;
    return n;
}

/* FNV-1a: two 64-bit constants and a multiply per byte. */
uint64_t fnv1a(const unsigned char *p, size_t n) {
    uint64_t h = 0xcbf29ce484222325u;
    for (size_t i = 0; i < n; i++) {
        h ^= p[i];
        h *= 0x100000001b3u;
    }
    return h;
}

/* Two counters in memory, each read, increased and written back. */
struct stats { long total; int counts[64]; };
void bump(struct stats *s, int i) {
    s->counts[i]++;
    s->total++;
}

The session compiles it with LLVM’s clang for x86-64, AArch64, RV64GC and RV64G (RISC-V without C), for size (-Os) and for speed (-O2), then reads each function’s bytes from the symbol table and counts its instructions:

"""Compiles five.c for four targets, then counts the bytes and the instructions of each function."""

import collections
import os
import pathlib
import re
import subprocess
import sys

sys.path.insert(0, str(pathlib.Path(__file__).parent / "sessions"))
import session

TARGETS = {
    "x86-64": "--target=x86_64-linux-gnu",
    "AArch64": "--target=aarch64-linux-gnu",
    "RV64GC": "--target=riscv64-linux-gnu -march=rv64gc",
    "RV64G": "--target=riscv64-linux-gnu -march=rv64g",
}
LEVELS = ("-Os", "-O2")  # optimised for size, then for speed

session.run("\n".join(
    [f"# The same file for four targets, optimised for size ({LEVELS[0]}), then for speed ({LEVELS[1]})"]
    + [f"clang-23 {flags} {level} -c five.c -o {name}{level}.o"
       for level in LEVELS for name, flags in TARGETS.items()]
    + ["# x86-64 once more, with indirect-branch tracking turned on",
       "clang-23 --target=x86_64-linux-gnu -Os -fcf-protection=full -c five.c -o x86-64-cet.o",
       "# The RISC-V objects keep one 64-bit constant of fnv1a outside the code",
       "llvm-size -A RV64GC-Os.o | grep -E '^[.](text|rodata)'"]
))

# The measuring tools are found the way the session above finds them.
ENV = dict(os.environ, PATH=os.pathsep.join([os.environ.get("PATH", ""), *session.EXTRA_BIN]))


def tool(*args: str) -> str:
    return subprocess.run(args, capture_output=True, text=True, env=ENV, check=True).stdout


def functions(obj: str) -> list[str]:
    """The functions an object file defines, in address order, so a function added to five.c is measured too."""
    names = []
    for line in tool("llvm-nm", "-S", "--defined-only", "-n", obj).splitlines():
        parts = line.split()
        if len(parts) == 4 and parts[2] in ("T", "t"):
            names.append(parts[3])
    return names


FUNCTIONS = functions(f"x86-64{LEVELS[0]}.o")


def measure(obj: str) -> dict[str, list[tuple[int, str]]]:
    """Returns the length in bytes and the mnemonic of every instruction of each function in one object file."""
    symbols = {}
    for line in tool("llvm-nm", "-S", "--defined-only", obj).splitlines():
        parts = line.split()
        if len(parts) == 4 and parts[3] in FUNCTIONS:
            symbols[parts[3]] = (int(parts[0], 16), int(parts[1], 16))
    found = collections.defaultdict(list)
    for line in tool("llvm-objdump", "-d", obj).splitlines():
        match = re.match(r"\s+([0-9a-f]+):\s+([0-9a-f ]+?)\s*\t(\S+)", line)
        if not match:
            continue
        address, size = int(match.group(1), 16), len(match.group(2).replace(" ", "")) // 2
        for name, (start, length) in symbols.items():
            if start <= address < start + length:
                found[name].append((size, match.group(3)))
    for name, (start, length) in symbols.items():
        assert sum(size for size, _ in found[name]) == length, (obj, name)  # every byte of the symbol was counted
    return found


def total(insns: list[tuple[int, str]]) -> str:
    return f"{sum(size for size, _ in insns)} / {len(insns)}"


print()
x86 = {}
for level in LEVELS:
    results = {name: measure(f"{name}{level}.o") for name in TARGETS}
    x86[level] = results["x86-64"]
    print(f"Bytes / instructions per function at {level}")
    print(f"{'function':<12}" + "".join(f"{name:>11}" for name in TARGETS))
    for function in FUNCTIONS:
        print(f"{function:<12}" + "".join(f"{total(r[function]):>11}" for r in results.values()))
    totals = [total([insn for insns in r.values() for insn in insns]) for r in results.values()]
    print(f"{'total':<12}" + "".join(f"{cell:>11}" for cell in totals))
    if level == LEVELS[0]:
        print(f"Instruction lengths at {level} (bytes: how many instructions)")
        for name, r in results.items():
            counts = collections.Counter(size for insns in r.values() for size, _ in insns)
            print(f"  {name:<8}", ", ".join(f"{size}: {n}" for size, n in sorted(counts.items())))
    print()

print(f"Where x86-64's extra bytes come from ({LEVELS[0]}, then {LEVELS[1]})")
for label, function, prefix in [("imul in fnv1a", "fnv1a", "imul"), ("div in gcd", "gcd", "div")]:
    counts = [sum(m.startswith(prefix) for _, m in x86[level].get(function, [])) for level in LEVELS]
    print(f"  {label + ':':<22}{counts[0]}, then {counts[1]}")
padding = [sum(size for insns in x86[level].values() for size, m in insns if m.startswith("nop")) for level in LEVELS]
print(f"  {'bytes of nop padding:':<22}{padding[0]}, then {padding[1]}")
print()

cet = measure("x86-64-cet.o")
print("x86-64 at -Os with -fcf-protection=full:", sum(size for insns in cet.values() for size, _ in insns), "bytes /",
      sum(map(len, cet.values())), "instructions")
print()
print("bump at -Os, instruction by instruction")
for name, flags in TARGETS.items():
    syntax = ["-M", "intel"] if name == "x86-64" else []
    listing = tool("llvm-objdump", "-d", "--no-addresses", *syntax, "--disassemble-symbols=bump", f"{name}-Os.o")
    lines = [line.strip() for line in listing.splitlines() if line.startswith((" ", "\t")) and line.strip()]
    print(f"  {name}:")
    for line in lines:
        print("    " + re.sub(r"\s+", " ", line))

# The same file for four targets, optimised for size (-Os), then for speed (-O2)
$ clang-23 --target=x86_64-linux-gnu -Os -c five.c -o x86-64-Os.o
$ clang-23 --target=aarch64-linux-gnu -Os -c five.c -o AArch64-Os.o
$ clang-23 --target=riscv64-linux-gnu -march=rv64gc -Os -c five.c -o RV64GC-Os.o
$ clang-23 --target=riscv64-linux-gnu -march=rv64g -Os -c five.c -o RV64G-Os.o
$ clang-23 --target=x86_64-linux-gnu -O2 -c five.c -o x86-64-O2.o
$ clang-23 --target=aarch64-linux-gnu -O2 -c five.c -o AArch64-O2.o
$ clang-23 --target=riscv64-linux-gnu -march=rv64gc -O2 -c five.c -o RV64GC-O2.o
$ clang-23 --target=riscv64-linux-gnu -march=rv64g -O2 -c five.c -o RV64G-O2.o
# x86-64 once more, with indirect-branch tracking turned on
$ clang-23 --target=x86_64-linux-gnu -Os -fcf-protection=full -c five.c -o x86-64-cet.o
# The RISC-V objects keep one 64-bit constant of fnv1a outside the code
$ llvm-size -A RV64GC-Os.o | grep -E '^[.](text|rodata)'
.text                  122      0
.rodata.cst8             8      0

Bytes / instructions per function at -Os
function         x86-64    AArch64     RV64GC      RV64G
gcd             36 / 14    40 / 10     20 / 9     36 / 9
clamp            13 / 6     20 / 5     18 / 7     28 / 7
skip_spaces      19 / 5     28 / 7     26 / 8     32 / 8
fnv1a           48 / 12    56 / 14    40 / 14    56 / 14
bump             11 / 4     32 / 8     18 / 9     36 / 9
total          127 / 41   176 / 44   122 / 47   188 / 47
Instruction lengths at -Os (bytes: how many instructions)
  x86-64   1: 5, 2: 11, 3: 17, 4: 3, 5: 2, 7: 1, 10: 2
  AArch64  4: 44
  RV64GC   2: 33, 4: 14
  RV64G    4: 47

Bytes / instructions per function at -O2
function         x86-64    AArch64     RV64GC      RV64G
gcd             54 / 21     32 / 8     16 / 7     28 / 7
clamp            13 / 6     20 / 5     24 / 9     36 / 9
skip_spaces      28 / 6     28 / 7     26 / 8     32 / 8
fnv1a          165 / 40    56 / 14    40 / 14    56 / 14
bump             11 / 4     32 / 8     18 / 9     36 / 9
total          271 / 77   168 / 42   124 / 47   188 / 47

Where x86-64's extra bytes come from (-Os, then -O2)
  imul in fnv1a:        1, then 5
  div in gcd:           1, then 2
  bytes of nop padding: 0, then 34

x86-64 at -Os with -fcf-protection=full: 147 bytes / 46 instructions

bump at -Os, instruction by instruction
  x86-64:
    48 63 c6 movsxd rax, esi
    ff 44 87 08 inc dword ptr [rdi + 4*rax + 0x8]
    48 ff 07 inc qword ptr [rdi]
    c3 ret
  AArch64:
    8b21c808 add x8, x0, w1, sxtw #2
    f940000a ldr x10, [x0]
    b9400909 ldr w9, [x8, #0x8]
    9100054a add x10, x10, #0x1
    f900000a str x10, [x0]
    11000529 add w9, w9, #0x1
    b9000909 str w9, [x8, #0x8]
    d65f03c0 ret
  RV64GC:
    058a slli a1, a1, 0x2
    95aa add a1, a1, a0
    6110 ld a2, 0x0(a0)
    4594 lw a3, 0x8(a1)
    0685 addi a3, a3, 0x1
    0605 addi a2, a2, 0x1
    e110 sd a2, 0x0(a0)
    c594 sw a3, 0x8(a1)
    8082 ret
  RV64G:
    00259593 slli a1, a1, 0x2
    00b505b3 add a1, a0, a1
    00053603 ld a2, 0x0(a0)
    0085a683 lw a3, 0x8(a1)
    00168693 addi a3, a3, 0x1
    00160613 addi a2, a2, 0x1
    00c53023 sd a2, 0x0(a0)
    00d5a423 sw a3, 0x8(a1)
    00008067 ret

At -Os, RV64GC is smallest with 122 bytes, then x86-64 with 127, AArch64 with 176 and RV64G with 188. Step through the functions to see where the bytes go:

Three effects explain the totals. Memory operands let x86-64 do in one instruction what a load/store ISA does in three, so bump is 11 bytes there. Fixed 4-byte instructions cost AArch64 bytes, not instructions: it needs fewer instructions than RISC-V in three of the five functions. RISC-V’s compressed forms make 33 of its 47 instructions 2 bytes long; without C the same instructions take 54 % more space.

The optimisation level moves the result more than the label does. At -O2, x86-64 grows to 271 bytes: the compiler unrolls the fnv1a loop four times, adds a 32-bit fast path to the 64-bit division and pads loop starts with 34 bytes of nop. The other targets change by 8 bytes or less. -fcf-protection=full adds a 4-byte endbr64 to each function, 20 bytes for five, as hardware control-flow integrity explains.

Practise

1. Cover the first section’s table, write its seven rows from memory, then compare.
2. Add a function to five.c that adds two 64-bit values in memory and stores the sum, predict the smallest target at -Os, then run size_session.py.
3. Replace -O2 with -Oz, clang’s smallest-code level, in size_session.py and compare the totals.

What four modelled cores make of the same instructions Pro: opens with a Pro, Premium or Ultimate pass

One base64 encoder written by hand for each ISA, counted and run Pro: opens with a Pro, Premium or Ultimate pass

Porting C between the ISAs, and choosing one for a job Pro: opens with a Pro, Premium or Ultimate pass

Interview questions

How does each of x86-64, AArch64 and RISC-V decide a conditional branch?

x86-64 branches on RFLAGS, which most arithmetic sets: cmp rax, rcx then jl. AArch64 branches on NZCV, which only flag-setting forms such as cmp and subs change, with b.lt, and cbz tests a register directly. RISC-V has no flags: blt a0, a1, label compares two registers inside the branch, and slt writes 0 or 1 when the result is needed as a value.

Three harder questions from the module’s bank: firmware that must shrink, a test that fails after a port, and an ISA for a device.

Key takeaways

• x86-64 has 1- to 15-byte instructions, memory operands and flags; AArch64 has 4-byte instructions, loads and stores only and flags on request; RISC-V has 4- or 2-byte instructions and no flags.
• For five C functions at -Os, RV64GC needed 122 bytes, x86-64 127, AArch64 176 and RV64G 188, so compressed forms mattered more than the CISC or RISC label.
• The optimisation level changed code size more than the ISA did: x86-64 grew from 127 to 271 bytes at -O2.
• Division by zero traps on x86-64, returns 0 on AArch64 and sets every bit on RISC-V.